1. Field of the Invention
The present invention relates to a PLL device, and more particularly to a PLL device with a current compensation circuit.
2. Description of the Related Art
The PLL devices have become the major element applying in the frequency generator, wireless receiver, communication device and so on. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional PLL device. PFD unit 11 receives a reference clock signal REF_CK and a feedback clock signal FBK_CK and measures the phase and frequency difference therebetween to output phase difference signals, UP and DN. Charging pump circuit 12 receives and transfers the phase difference signals UP and DN into a current to charge loop filter 13. In FIG. 1, a circuit of a conventional loop filter 13 is provided. The loop filter 13 receives the current from charging pump circuit to limit the rate of change of a capacitor voltage, VCON, resulting in slow rising or falling voltage corresponding to the phase and frequency difference. The voltage controlled oscillator (VCO) 14 generates an output clock signal according to the voltage VCON. Feedback divider 15 has a parameter N to generate the feedback clock signal FBK_CK with wider range frequency, wherein the frequency of the feedback clock signal FBK_CK is N times the frequency of the output clock signal. In an ideal situation, when the PLL is in in-lock state, the phase difference signal UP synchronizes to the phase difference signal DN. If a leakage current is generated in loop filter 13, such as the currents I1 and I2, the charging time of capacitor C2 increases, thus the phase difference signal. UP leads to the phase difference signal DN. Please refer to FIG. 2. FIG. 2 is a waveform of the phase difference signal UP and phase signal DN of FIG. 1. Since a leakage current is generated in the loop filter 13, the charging time of capacitor C2 increases, thus the width of phase difference signal UP is wider than the width of phase difference signal DN, and a phase lead signal LEAD is generated. To optimize the performance of the PLL device, eliminating the generating of phase lead signal LEAD is indeed required. In the semiconductor process, the capacitor C1 and C2 are formed by transistors, if the transistors are formed by 0.18 μm, 0.13 μm or other advanced processes, leakage current may be generated due to the thin gate oxide. However, the thin gate oxide manufactured by the semiconductor process is inevitable, thus a PLL device capable of reducing or eliminating the leakage current of the loop filter thereof is desirable.